This invention relates to a charge-coupled device having a series register and a parallel section, for example a charge-coupled device suitable for use as a series-parallel-series (SPS) memory device.
Charge-coupled devices are known which have a series register having charge storage electrodes for defining charge storage wells and charge transfer electrodes for transporting charge between the charge storage wells and a parallel section having channels extending transversely of the series register. The parallel section has charge storage electrodes spaced apart along the channels, each charge storage electrode extending transversely over the channels to define a respective charge storage well with each channel to provide a respective row of charge storage wells extending transversely of the channel. The parallel section also has charge transfer electrodes for transferring charge between adjacent rows of charge storage wells. A transfer gate is provided for transferring charge between the series register and an adjacent row of charge storage wells defined by the channels and a first charge storage electrode of the parallel section. Such charge-coupled devices may comprise part of a series-parallel-serial (SPS) charge-coupled device in which a further series register is provided so that one series register forms an input series register and the other an output series register of the device. Such SPS charge-coupled devices which are suitable for use as memories in which the channels of the parallel section form a memory matrix for analog or digital information which is introduced via the series input register and which can be read out via the series output register. Another form of charge-coupled device of the above-described type is an image sensor in which the charge stored in the parallel section corresponds to a received two-dimensional radiation pattern.
GB-B-2110874 describes such a charge-coupled device which may comprise an SPS memory device. As described in GB-B-2110874, the charge storage and charge transfer electrodes are provided as a two-level conductive pattern on a dielectric layer of the semiconductor body overlying a surface region of the semiconductor body in which the channels and charge wells are provided. The upper level providing the charge transfer electrode is of course insulated by dielectric material from the lower level providing the charge storage electrodes. As described in GB-B-2110874, the two-level conductive pattern is provided by depositing and patterning first and second layers of doped polycrystalline silicon. Although other conductive material, for example a metal such as aluminum may be used, the use of polycrystalline silicon has the advantage of enabling the use of thinner dielectric layers.